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high voltage, latch-up proof, 4-channel multiplexer ADG5404 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2011 analog devices, inc. all rights reserved. features latch-up proof 8 kv hbm esd rating low on resistance (<10 ) 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications relay replacement automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagram s 1 1 of 4 decoder ADG5404 s 2 d s 3 s 4 a0 a1 en 09203-001 figure 1. general description the ADG5404 is a complementary metal-oxide semiconductor (cmos) analog multiplexer, comprising four single channels. the on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. the ADG5404 is designed on a trench process, which guards against latch-up. a dielectric trench separates the p and n channel transistors, thereby preventing latch-up even under severe overvoltage conditions. the ADG5404 switches one of four inputs to a common output, d, as determined by the 3-bit binary address lines, a0, a1, and en. logic 0 on the en pin disables the device. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condi- tion, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. low r on . 3. dual-supply operation. for applications where the analog signal is bipolar, the ADG5404 can be operated from dual supplies of up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the ADG5404 can be operated from a single-rail power supply of up to 40 v. 5. 3 v logic-compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
ADG5404 rev. a | page 2 of 20 table of contents functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 +12 v single supply ..................................................................... 5 +36 v single supply ..................................................................... 6 continuous current per channel, s or d ................................. 7 absolute maximum ratings............................................................ 8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 truth table .....................................................................................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 14 terminology .................................................................................... 17 trench isolation.............................................................................. 18 applications information .............................................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 7/11rev. 0 to rev. a changes to product highlights....................................................... 1 change to i ss parameter, table 2..................................................... 4 updated outline dimensions ....................................................... 20 7/10revision 0: initial version
ADG5404 rev. a | page 3 of 20 specifications 15 v dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9.8 typ v s = 10 v, i s = ?10 ma; see figure 23 11 14 16 max v dd = +13.5 v, v ss = ?13.5 v on-resistance match between channels, ?r on 0.35 typ v s = 10 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat(on) 1.2 typ v s = 10 v, i s = ?10 ma 1.6 2 2.2 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.05 na typ v s = v s = 10 v, v d = ? 10 v; see figure 24 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.1 na typ v s = v s = 10 v, v d = ? 10 v; see figure 24 0.4 2 12 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 10 v; see figure 25 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 187 ns typ r l = 300 , c l = 35 pf 242 285 330 ns max v s = 10 v; see figure 30 t on (en) 160 ns typ r l = 300 , c l = 35 pf 204 247 278 ns max v s = 10 v; see figure 32 t off (en) 125 ns typ r l = 300 , c l = 35 pf 145 168 183 ns max v s = 10 v; see figure 32 break-before-make time delay, t d 45 ns typ r l = 300 , c l = 35 pf 12 ns min v s1 = v s2 = 10 v; see figure 31 charge injection, q inj 220 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 33 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 26 channel-to-channel crosstalk ?58 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.009 % typ r l = 1k , 15 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 53 mhz typ r l = 50 , c l = 5 pf; see figure 27 insertion loss ?0.7 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 19 pf typ v s = 0 v, f = 1 mhz c d (off) 92 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 132 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/max gnd = 0 v 1 guaranteed by design; not subject to production test.
ADG5404 rev. a | page 4 of 20 20 v dual supply v dd = 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9 typ v s = 15 v, i s = ?10 ma; see figure 23 10 13 15 max v dd = +18 v, v ss = ?18 v on-resistance match between channels, ?r on 0.35 typ v s = 15 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat(on) 1.5 typ v s = 15 v, i s = ?10 ma 1.8 2.2 2.5 max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off) 0.05 na typ v s = 15 v, v d = ? 15 v; see figure 24 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.1 na typ v s = 15 v, v d = ? 15 v; see figure 24 0.4 2 12 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 15 v; see figure 25 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 175 ns typ r l = 300 , c l = 35 pf 224 262 301 ns max v s = +10 v; see figure 30 t on (en) 148 ns typ r l = 300 , c l = 35 pf 185 222 250 ns max v s = 10 v; see figure 32 t off (en) 120 ns typ r l = 300 , c l = 35 pf 142 159 173 ns max v s = 10 v; see figure 32 break-before-make time delay, t d 40 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 31 charge injection, q inj 290 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 33 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 26 channel-to-channel crosstalk ?58 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.008 % typ r l = 1 k, 20 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 54 mhz typ r l = 50 , c l = 5 pf; see figure 27 insertion loss ?0.6 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 18 pf typ v s = 0 v, f = 1 mhz c d (off) 88 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 129 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/max gnd = 0 v 1 guaranteed by design; not subject to production test.
ADG5404 rev. a | page 5 of 20 +12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 19 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 23 22 27 31 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels, ?r on 0.4 typ v s = 0 v to 10 v, i s = ?10 ma 0.8 1 1.2 max on-resistance flatness, r flat(on) 4.4 typ v s = 0 v to 10 v, i s = ?10 ma 5.5 6.5 7.5 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 24 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.05 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 24 0.4 2 12 na max channel on leakage, i d , i s (on) 0.05 na typ v s = v d = 1 v/10 v; see figure 25 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 266 ns typ r l = 300 , c l = 35 pf 358 446 515 ns max v s = +8 v; see figure 30 t on (en) 260 ns typ r l = 300 , c l = 35 pf 339 423 485 ns max v s = 8 v; see figure 32 t off (en) 135 ns typ r l = 300 , c l = 35 pf 162 189 210 ns max v s = 8 v; see figure 32 break-before-make time delay, t d 125 ns typ r l = 300 , c l = 35 pf 45 ns min v s1 = v s2 = 8 v; see figure 31 charge injection, q inj 92 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 33 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1mhz; see figure 26 channel-to-channel crosstalk ?58 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.075 % typ r l = 1k , 6 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 43 mhz typ r l = 50 , c l = 5 pf; see figure 27 insertion loss ?1.36 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 22 pf typ v s = 6 v, f = 1 mhz c d (off) 105 pf typ v s = 6 v, f = 1 mhz c d , c s (on) 140 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
ADG5404 rev. a | page 6 of 20 +36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 10.6 typ v s = 0 v to 30 v, i s = ?10 ma; see figure 23 12 15 17 max v dd = 32.4 v, v ss = 0 v on-resistance match between channels, ?r on 0.35 typ v s = 0 v to 30 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat(on) 2.7 typ v s = 0 v to 30 v, i s = ?10 ma 3.2 3.8 4.5 max leakage currents v dd =39.6 v, v ss = 0 v source off leakage, i s (off) 0.05 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 24 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.1 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 24 0.4 2 12 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 1 v/30 v; see figure 25 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 196 ns typ r l = 300 , c l = 35 pf 256 276 314 ns max v s = 18 v; see figure 30 t on (en) 170 ns typ r l = 300 , c l = 35 pf 214 247 273 ns max v s = 18 v; see figure 32 t off (en) 130 ns typ r l = 300 , c l = 35 pf 172 167 176 ns max v s = 18 v; see figure 32 break-before-make time delay, t d 52 ns typ r l = 300 , c l = 35 pf 13 ns min v s1 = v s2 = 18 v; see figure 31 charge injection, q inj 280 pc typ v s = 18 v, r s = 0 , c l = 1 nf; see figure 33 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1mhz; see figure 26 channel-to-channel crosstalk ?58 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.03 % typ r l = 1k , 18 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 47 mhz typ r l = 50 , c l = 5 pf; see figure 27 insertion loss ?0.85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 c s (off) 18 pf typ v s = 18 v, f = 1 mhz c d (off) 89 pf typ v s = 18 v, f = 1 mhz c d , c s (on) 128 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
ADG5404 rev. a | page 7 of 20 continuous current per channel, s or d table 5. parameter 25c 85c 125c unit continuous current, s or d v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 165 96 49 ma max lfcsp ( ja = 30.4c/w) 290 141 57 ma max v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 176 101 51 ma max lfcsp ( ja = 30.4c/w) 282 146 58 ma max v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 114 72 42 ma max lfcsp ( ja = 30.4c/w) 203 112 53 ma max v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 149 89 48 ma max lfcsp ( ja = 30.4c/w) 263 133 56 ma max
ADG5404 rev. a | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or d pins 515 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s or d 2 data + 15% operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c thermal impedance, ja 16-lead tssop, ja thermal impedance (4-layer board) 112.6c/w 16-lead lfcsp, ja thermal impedance (4-layer board) 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c only one absolute maximum rating can be applied at any one time. esd caution 1 overvoltages at the sx and d pins ar e clamped by internal diodes. limit current to the maximum ratings given. 2 see . table 5
ADG5404 rev. a | page 9 of 20 pin configurations and function descriptions ADG5404 nc = no connect 1 2 3 4 5 6 7 en v ss s1 nc d s2 a0 14 13 12 11 10 9 8 gnd v dd s3 nc nc s4 a1 top view (not to scale) 09203-002 figure 2. tssop pin configuration pin 1 indicator notes 1. nc = no connect. 2 . exposed pad tied to substrate, v ss . 1v ss 2 nc 3 s1 4 s2 11 v dd 12 gnd 10 s3 9s4 5 nc 6 d 7 nc 8 nc 15 a0 16 en 14 a1 13 nc top view (not to scale) ADG5404 09203-003 figure 3. lfcsp pin configuration table 7. pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, the ax logi c inputs determine the on switches. 3 1 v ss most negative power supply potential. 4 3 s1 source terminal. can be an input or an output. 5 4 s2 source terminal. can be an input or an output. 6 6 d drain terminal. can be an input or an output. 7 to 9 2, 5, 7, 8, 13 nc no connection. 10 9 s4 source terminal. can be an input or an output. 11 10 s3 source terminal. can be an input or an output. 12 11 v dd most positive power supply potential. 13 12 gnd ground (0 v) reference. 14 14 a1 logic control input. ep exposed pad the exposed pad is connected internally. for in creased reliability of the solder joints and maximum thermal capability, it is recommended th at the pad be soldered to the substrate, v ss . truth table table 8. en a1 a0 s1 s2 s3 s4 0 x 1 x 1 off off off off 1 0 0 on off off off 1 0 1 off on off off 1 1 0 off off on off 1 1 1 off off off on 1 x = dont care.
ADG5404 rev. a | page 10 of 20 typical performance characteristics 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +11v v ss = ?11v 09203-029 figure 4. r on as a function of v d (v s ), dual supply 0 2 4 6 8 10 12 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09203-030 figure 5. r on as a function of v d (v s ), dual supply 0 5 10 15 20 25 02468101214 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = 0v v dd = +10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 11v v ss = 0v v dd = 13.2v v ss = 0v v dd = 12v v ss = 0v 09203-027 figure 6. r on as a function of v d (v s ), single supply 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 40 45 on resistance ( ? ) t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v v s , v d (v) 09203-028 figure 7. r on as a function of v d (v s ), single supply 09203-023 0 2 4 6 8 10 12 14 18 16 ?15 ?10 ?5 0 5 10 15 on resistance ( ? ) v s , v d (v) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = +15v v ss = ?15v figure 8. r on as a function of v d (v s ) for different temperatures, 15 v dual supply 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09203-024 figure 9. r on as a function of v d (v s ) for different temperatures, 20 v dual supply
ADG5404 rev. a | page 11 of 20 0 5 10 15 20 25 30 024681012 on resistance ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v vs, vd (v) 09203-025 figure 10. r on as a function of v d (v s ) for different temperatures, 12 v single supply 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 on resistance ( ? ) v s , v d (v) v dd = 36v v ss = 0v 09203-026 t a = +125c t a = +85c t a = +25c t a = ?40c figure 11. r on as a function of v d (v s ) for different temperatures, 36 v single supply 0 25 50 75 100 125 leakage current (na) 1.0 ?1.0 0.5 ?0.5 ?1.5 0 i d , i s (on) ? ? i d (off) + ? i s (off) ? + i d , i s (on) + + i s (off) + ? i d (off) ? + v dd = +15v v ss = ?15v v bias = +10v/?10v temperature (c) 09203-032 figure 12. leakage currents vs. temperature, 15 v dual supply 0 255075100125 leakage current (na) temperature (c) 1.0 ?1.0 0.5 ?2.0 ?0.5 ?1.5 0 v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) ? + i d (off) ? + i s (off) + ? 09203-033 figure 13. leakage currents vs. temperature, 20 v dual supply 0 255075100125 leakage current (na) temperature (c) 0.6 ?0.2 0.4 ?0.6 0 ?0.4 0.2 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i s (off) ? + i d (off) ? + 09203-031 figure 14. leakage currents vs. temperature, 12 v single supply 1.0 ?1.0 0.5 ?2.0 ?0.5 ?1.5 0 0 25 50 75 100 125 leakage current (na) temperature (c) v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i d , i s (on) ? ? i d (off) + ? i s (off) + ? i s (off) ? + i d (off) ? + 09203-034 figure 15. leakage currents vs. temperature, 36 v single supply
ADG5404 rev. a | page 12 of 20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 off isolation (db) frequency (hz) 1k 10k 100k 1m 10m 100m 1g t a = 25c v dd = +15v v ss = ?15v 09203-019 figure 16. off isolation vs. frequency, 15 v dual supply ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 crosstalk (db) frequency (hz) 100k 1m 10m 100m 1g 10k t a = 25c v dd = +15v v ss = ?15v 09203-016 figure 17. crosstalk vs. frequency, 15 v dual supply ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 insertion loss (db) frequency (hz) 10k 100k 1m 10m 1k 100m t a = 25c v dd = +15v v ss = ?15v 09203-020 figure 18. on response vs. frequency, 15 v dual supply 50 100 150 200 250 300 350 400 450 ?20?100 10203040 charge injection (pc) v s (v) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = 36v v ss = 0v v dd = 12v v ss = 0v 09203-021 figure 19. charge injection vs. source voltage 0 50 100 150 200 250 300 350 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) v dd = +12v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +36v, v ss = 0v v dd = +20v, v ss = ?20v 09203-022 figure 20. transition time vs. temperature acpsrr (db) frequency (hz) 1k 1m 10m 10k 100k ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 t a = 25c v dd = +15v v ss = ?15v decoupling capacitors no decoupling capacitors 09203-017 figure 21. acpsrr vs. frequency, 15 v dual supply
ADG5404 rev. a | page 13 of 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 5 10 15 20 thd + n (%) frequency (mhz) load = 1k ? t a = 25c v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 36v, v ss = 0v, v s = 18v p-p v dd = 15v, v ss = 15v, v s = 15v p-p v dd = 20v, v ss = 20v, v s = 20v p-p 09203-018 figure 22. thd + n vs. frequency, 15 v dual supply
ADG5404 rev. a | page 14 of 20 test circuits i ds sx d v s v 09203-005 figure 23. on resistance v s v d sx d a a i s (off) i d (off) 09203-006 figure 24. off leakage sx d a v d i d (on) nc nc = no connect 09203-007 figure 25. on leakage v out 50? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? off isolation = 20 log v out v s 09203-008 figure 26. off isolation v out 50? network analyzer r l 50 ? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd insertion loss = 20 log v out with switch v out without switch 09203-009 figure 27. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r l 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 09203-010 figure 28. channel-to-channel crosstalk
ADG5404 rev. a | page 15 of 20 v out r s audio precision r l 1k ? in v in sx d v s v p-p 0.1f v dd 0.1f v ss v dd v ss gnd 09203-011 figure 29. thd + noise v dd v ss v dd v ss v in s1 d gnd c l 35pf r l 300 ? v out v out 50% 50% 90% 90% address drive (v in ) ) a0 a1 s4 s3 s2 v s1 v s4 en 2.4v 0v 3v t transition t transition 0.1f 0.1f 09203-012 figure 30. address to output switching times v dd v ss v dd v ss c l 35pf r l 300 ? address drive (v in ) v out v out v in s1 d gnd 300 ? a0 a1 s4 s3 s2 v s1 en 2.4v 0.1f 0.1f t bbm 80% 80% 0v 3v 09203-013 figure 31. break-before-make time delay
ADG5404 rev. a | page 16 of 20 enable drive (v in ) s1 d gnd c l 35pf r l 300 ? a0 a1 s4 s3 s2 en 0.1f 0.1f v in 300 ? t off (en) t on (en) 50% 50% 0.9v out 0.9v out output 0v 3v v out 0v v dd v ss v dd v ss v s v out 09203-014 figure 32. enable-to-output switching delay sx d v s gnd r s sw off sw off sw on sw off sw off a2a1 en v dd v ss v dd decoder v ss v out v out v in v in ? v out c l 1nf q inj = c l ? v out 09203-015 figure 33. charge injection
ADG5404 rev. a | page 17 of 20 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t transition the delay time between the 50% and 90% points of the digital input and switch-on condition when switching from one address state to another. t on (en) the delay between applying the digital control input and the output switching on. see figure 32 . t off (en) the delay between applying the digital control input and the output switching off. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n the ratio of the harmonic amplitude plus noise of the signal to the fundamental. acpsrr (ac power supply rejection ratio) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the parts ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
ADG5404 rev. a | page 18 of 20 trench isolation in the ADG5404, an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a completely latch-up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode can become forward-biased. a silicon-controlled rectifier (scr) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. with trench isolation, this diode is removed, and the result is a latch-up proof switch. nmos pmos p-well n-well buried oxide layer handle wafer trench 09203-004 figure 34. trench isolation
ADG5404 rev. a | page 19 of 20 applications information the adg54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. the ADG5404 high voltage multiplexer allows single-supply operation from 9 v to 40 v and dual-supply operation from 9 v to 22 v. the ADG5404, as well as three other adg54xx family members, adg5412 / adg5413 and adg5436 , achieve an 8 kv human body model esd rating that provides a robust solution and eliminates the need for separate protection circuitry designs in some applications.
ADG5404 rev. a | page 20 of 20 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 35. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 36. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADG5404bruz ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ADG5404bruz-reel7 ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ADG5404bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-17 1 z = rohs compliant part. ?2010C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09203-0-7/11(a)

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